It is common practice to mount integrated circuit chips onto substrates carrying film circuits or printed circuits. In some cases the integrated circuit chip is mounted face upward--that is with its array of connection contact areas uppermost--and connection between the contact areas and conductor lands on the substrate is made by means of thin jumper wires which extend over the edges of the chip. See, e.g., U.S. Pat. Nos. 3,082,327 and 3,011,379.
In other cases--commonly referred to as "flip-chip"--the chip is mounted face downwards and its contact areas are bonded to respective conductor lands on the substrate. See e.g., U.S. Pat. No. 3,292,240.
A variety of methods have been used for joining the contact areas of the chip to the respective conductor lands or jumper wires. The chip may include an integrated circuit having a plurality of separate or structurally integrated transistors, diodes, resistors and capacitors formed in the monolithic body of semiconductor material. Problems common to many prior art structures where chips are mounted on a substrate is to achieve an assembly providing adequate cooling, ability to withstand thermal shock and mechanical forces.
Numerous integrated circuit packaging structures are known in the prior art. The following prior art patents, publications and summaries are submitted to generally represent the state of the prior art.
U.S. Pat. No. 3,325,882 entitled "Method for Forming Electrical Connections to a Solid State Device Including Electrical Packaging Arrangement Therefor" granted June 20, 1967 to C. Chiou et al.
U.S. Pat. No. 3,487,541 entitled "Printed Circuits" granted Jan. 6, 1970 to D. Boswell. The Boswell patent discloses a process for manufacturing a mounted semiconductor device assembly having a die of semiconductor material secured to a substrate with a set of contact fingers joining respective electrode contact areas on the die to corresponding conductor lands on the substrate, the fingers extending over and/or under the die.
U.S. Pat. No. 3,544,857 entitled "Integrated Circuit Assembly with Lead Structure and Method" granted Dec. 1, 1970 to R. C. Byrne et al. The integrated circuit assembly with lead structure consists of a semiconductor body having at least portions of an electrical circuit formed therein and with contact pads carried by the body and lying in a common plane with leads carried by the body connecting the circuit to the pads. Support means is provided, at least a portion of which is formed of insulating material a plurality of spaced metallic leads are carried by the support means and are insulated from each other by the support means. The leads have contact areas arranged in a pattern lying in a common plane. A plurality of connecting elements of thin metallic film are in direct and intimate contact with the contact pads whereby the thin film connecting elements form the sole means for making electrical contact between the leads and the contact pads so that electrical contact may be made to the portions of the electrical circuit through the leads. In certain embodiments of the Byrne et al patent the connecting elements are carried by a flexible plastic tab or member.
U.S. Pat. No. 3,614,832 entitled "Decal Connectors and Methods of Forming Decal Connections to Solid State Devices" granted Oct. 26, 1971 D. A. Chance et al. A plurality of connections from electrically conductive lands on an insulating substrate to the contacts of a solid state device are formed in one operation by fixedly positioning the device on, or in a cavity within, the substrate. A decal, including a backing plate with a plurality of conductive strips which can be adhered to the plate by means of a soluble adhesive, is positioned over the device bearing substrate with the strips in registry with respective contacts and lands. The strips are brought into contact with respective contact and land surface portions and subjected to heat and pressure sufficient to cause bonding therebetween. Thereafter, the decal backing plate may be removed from the strips, as by dissolving the adhesive, leaving the strips firmly bonded to the contacts and lands and bridging the space therebetween, whereby the lands are connected to the contacts through the strips.
U.S. Pat. No. 3,662,230 entitled "A Semiconductor Interconnecting System Using Conductive Patterns Bonded to Thin Flexible Insulating Films" granted May 9, 1972 to J. O. Redwantz. The Redwantz patent discloses packaging system for one or more semiconductor chips each having metal contact pads on at least one face. A rigid support is provided for the semiconductor chip and also the large leads which are used to connect the packaged device in an external circuit. A set of thin metallic film strips are bonded to a thin flexible dielectric sheet for support. The set of metal strips interconnects the contact pads on the semiconductor chips and selected leads to electrically interconnect the semiconductor device and the leads. Where a plurality of semiconductor devices are used, a plurality of dielectric sheets can be stacked and electrical connections made between the different layers of metal film strips through openings in the dielectric sheets. Several processes for assembling the packages are also described.
U.S. Pat. No. 3,757,175 entitled "Composite Integrated Circuits with Coplanar Connections to Semiconductor Chips Mounted on a Single Substrate" granted Sept. 4, 1973 to C. S. Kim et al. The Kim et al patent discloses a structure which includes a rigid dielectric substrate for supporting a number of semiconductor chips having metallized contact electrodes and an insulating material overlaying one surface of the substrate in which material said chips are embedded. The substrate further supports conductor strips having terminal electrodes intended to be connected to said contact electrodes. The chips are bonded to the substrate with said contact electrodes in registry with said terminal electrodes and with the contact and terminal electrodes contiguous with the surface of said insulating material. Metallization deposited on the surface of the insulating material extending between the contact and terminal electrodes forms electrical connections to the chips.
U.S. Pat. No. 3,780,352 entitled "Semiconductor Interconnecting System Using Conductive Patterns Bonded to Thin Flexible Insulating Films" granted Dec. 18, 1973 to J. O. Redwantz. The Redwantz patent discloses a packaging system for one or more semiconductor chips each having metal contact pads on at least one face. A rigid support is provided for the semiconductor chip and also the large leads which are used to connect the packaged device in an external circuit. A set of thin metallic film strips are bonded to a thin flexible dielectric sheet for support. The set of metal strips interconnect the contact pads on the semiconductor chips and selected leads to electrically interconnect the semiconductor device and the leads. Where a plurality of semiconductor devices are used a plurality of dielectric sheets can be stacked and electrical connections made between the different layers of metal film strips through openings in the dielectric sheets. Processes for assembling the packages are also described.
U.S. Pat. No. 3,781,596 entitled "Semiconductor Chip Carriers and Strips Thereof" granted Dec. 25, 1973 to R. J. Galli et al. The Galli et al patent discloses "a method of interconnecting semiconductor chips to the circuitry of a substrate package by means of a flexible transparent carrier". The carrier is composed of a film base upon which there is a pattern of discretionary conductors and bonding pads. The film serves as a supporting layer for the conductor pattern which is applied to one surface thereof by selective deposition and/or etching of coatings and raised contact areas. Chips are mounted so that the active chip surface is bonded to the carrier pads, and thereafter connected to the circuitry of the substrate by the discretionary carrier conductor pattern. The carrier pads localized the bonding contact area for reliable bonding and raise the carrier conductors of the active surface of the chip to prevent shorting. The optional registration holes of the carrier film provide means for accurate alignment of chips and carrier contact area.
U.S. Pat. No. 3,805,375 entitled "Composite Integrated Circuits Including Semiconductor Chips Mounted on A Common Substrate with Connections Made Through A Dielectric Encapsulator" granted Apr. 23, 1974 to D. J. La Combe et al. The La Combe et al patent discloses a structure which includes a rigid dielectric substrate for supporting a number of integrated circuit semiconductor chips having metallized contact electrodes on one or more faces thereof. The substrate further supports conductor strips having terminal electrodes intended to be connected to said contact electrodes. The chips are bonded to the substrate with said contact electrodes in registry with said terminal electrodes. An encapsulating dielectric material overlays said substrate and semiconductor chips. Openings are formed within said dielectric material which are in alignment with said contact and terminal electrodes. Metallization deposited on the surface of said dielectric material enters said openings and makes electrical connection between the conductor strips on said substrate and the semiconductor chips.
U.S. Pat. No. 3,999,285 entitled "Semiconductor Device Package" granted June 30, 1975 to T. E. Lewis et al. The Lewis et al patent is directed to an integrated circuit semiconductor device package and a method of making it. A woven fiber mat impregnated with an epoxy adhesive serves as a first housing member. It includes an opening therein for receiving an integrated circuit semiconductor device. The housing member is placed on a supporting heat sink and a lead frame placed on top of the housing member. This sub assembly is heated to bond the elements together by curing the epoxy adhesive in the first housing member. A second housing member is then placed over the lead frame. The second housing member includes an opening therein which is slightly larger than the opening in the first housing member. A lid is placed on top of the second housing member to cover the opening after the semiconductor device has been bonded to the substrate within the openings in the housing members. The assembly is then heated to bond the remaining elements together with the epoxy adhesive in the second housing member to form a completed package.
U.S. Pat. No. 4,012,832 entitled "Method for Non-Destructive Removal of Semiconductor Devices" granted Mar. 22, 1977 to J. R. Crane. Semiconductor devices having a conductive lead pattern on the bottom of the device are bonded to conductive pads on a substrate to form an electrical connection therewith. The connection comprises two layers of conductive adhesive plastic separated by a small chip of conductive alloy which melts above the curing temperature of the adhesive plastic. The non-destructive removal of a semiconductor device from the substrate is accomplished by heating only the semiconductor device to be removed until the alloy chip under the device melts, thus, permitting the non-destructive removal of the semiconductor device without the application of force which would tend to destroy the semiconductor device.
Reference is made to the following IBM Technical Disclosure Bulletin Publications:
"Joining Semiconductor Chips to A Decal Interconnection Overlay" by F. J. Kurtz, Vol. 11, No. 3, August 1968, page 309; "Multichip Packaging" by P. Ehret et al., Vol. 14, No. 10, March 1972, page 3090; 137 Matched Expansion Chip Package" by V. D. Van Vestrout, Vol. 16, No. 3, August 1973, page 758; and "Processing PC Conductor Decals" by C. E. Gazdik et al., Vol. 21, No. 11, April 1979, page 4425. The immediately foregoing publication discloses the flip-chip bonding of semiconductor chips to thin flexible polyimide substrates or printed circuit decals.
Reference is made to the IBM Technical Disclosure Bulletin publication entitled "Semiconductor Die with Wiring Skirt (Packaging Structure)" by M. Ecker and L. Olson, Vol. 21, No. 2, July 1978. This publication, by the applicants' of this application, discloses the structure disclosed and claimed herein.
The invention may be summarized as an improved packaging structure wherein one or more integrated circuit chips are mounted on membrane-like insulating members. The membrane-like members provide multilevel wiring and interconnection between the chip or chips and a secondary wiring structure. The packaging structure includes a module protective cap (preferably metal) and resilient means supported by said secondary wiring structure. The resilient means physically biases the semiconductor chip or chips against the module protective cap and also accommodates induced chip motion and variation. The packaging structure provides enhanced thermal, mechanical and electrical characteristics.
The primary object of the invention is an improved integrated circuit chip packaging structure having enhanced thermal, mechanical and electrical characteristics.